|
Lecture May 26 16:05 |
The increasing design complexity along with the emergence of new failure mechanisms in the nanometer regime has significantly increased the complexity of manufacturing ramp of ICs. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced to 90 nanometer and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered.
Marginal circuit behaviour may limit operation of the design at some operating conditions. Additionally, optimizing the performance and power of the design for the intended applications typically required some learning on silicon. Some of these issues are only uncovered post-silicon due to limitations of the pre-silicon design and validation effort, and require efficient manufacturing debug techniques.
This lecture will provide a detailed understanding of the state-of-the-art in manufacturing debug and diagnosis techniques used by the industry today, and the research and development challenges ahead.
Basic understanding of digital design, BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
This test clinic will provide newcomers to test and students pursuing graduate studies a broad but comprehensive overview of topics like Silicon Debug, Diagnosis, DFM and variability, and how they relate directly to manufacturing test and post-silicon validation. It will also be of interest to IC Designers; test, DFT, and product engineers; DA developers; validation, debug, and failure analysis engineers; researchers, managers, and anyone else determined to shorten the time-to-volume of a newly manufactured chip.
Introduction
What is Yield?
Sources of Yield loss – Random, Systematic and Parametric, Defect versus design-related
What is DFX? Interaction of manufacturability, yield, variability, and test
What is DFM?
Manufacturing test and diagnosis
How does a Fab improve defectivity and manage yield? Fab Metrology, In-line inspections, Process control, Test chips and Test structures
DFM Enhancement Techniques
Variability and defects
The relationship between test and yield
Manufacturing and Defect aware tests, DFM-oriented tests,Timing aware tests
Basics of logic, scan chain and memory diagnosis
Diagnosis of Delay Faults and Timing Errors
Defect learning from test and diagnosis
Post-silicon circuit-level debug
Debugging Clocking Issues
Debug of Power Issues
Hardware probing techniques
Summary and conclusion
References