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Lecture May 27 14:00 |
While integration is forcing more and more logic into the components, being able to extract all of the data that is being generated inside the component and delivering it to another component, board or system is critical to the operation of the system/network. The bandwidth at which data is generated or required is challenging board and system designers. Data is being driven across networks at tens of Gigabits per second. These speeds will increase to hundreds of Gigabits per second in the next 3 – 5 years. In addition, the massive amounts of logic integration, enabled by technology scaling, is creating unmanageable complexity at the component level. Verifying that components meet their specifications is becoming more and more difficult. Testing these components in a board or system environment is even more challenging.
Given that much of the logic/memory integration will be incorporated into the components, the design aspect of this lecture will focus primarily on delivering high speed signals on board from component to component and from component to external interfaces. Significant attention will be given to signal and power integrity and their impact on performance. In addition, new advances such as silicon photonics and optical interconnects will also be discussed along with their ramifications to board level design and system level performance.
From a test perspective, the lecture will cover defects and failures in both digital (logic) and analog (high speed signalling) circuits. The lecture will discuss how defects are manifested into failures and what can be done to detect failures and isolate them to the corresponding defect. The lecture will look at an “Industry Best Practices” test flow and talk about test challenges which are a result of logic complexity and ultra-high data rates. The lecture will consider challenges in defect detection, localization and isolation from a system level to a component level (all of these impact the quality and reliability of the printed circuit assembly). Innovative approaches to debug and diagnosis will also be covered.
BSEE or BSCS; Basic understanding of digital design; some understand of high speed signaling would be beneficial. Suggested reading would include: System on Chip Test Architectures, Wang, Stroud, Touba; The Boundary-Scan Handbook (2003), Parker; High Speed Signal Propagation: Advanced Black Magic, Johnson, Graham; A Signal Integrity Engineers Companion: Real-Time Test and Measurement and Design Simulation; “Design for Board and System Level Structural Test and Diagnosis, Vo et al., IEEE International Test Conference, 2006.
The student will gain a basic understanding of board level design; test and debug of components, boards and systems, including high speed signal design and test. The student will understand the “practical” aspects of design and test, including industry standards and best practices. Students will also get exposure to new and significant topics in the area, including research.
- Overview – current architectures and design/test impacts:
- Component Scaling/Technology integration
- High Speed Signalling – up to 100G
- Board Design Considerations
- Layout – trace density, timing
- Signal Integrity
- Power/Thermal
- Manufacturing Process and Defect Opportunities
- Component level Defects
- Board Level Defects
- System Level Defects
- Manufacturing Test Process Overview/Effectiveness
- DFT and Test
- Built-in Self-Test
- DFT assisted Functional Tests
- Abstraction in property checking
- Integrating property checking into SoC design flow