Fault Models, Fault Simulation and Test Generation

Lecture

May 22 14:00
Mariapoli

Vishwani Agrawal
Auburn University

These lectures are selected from a full-semester graduate-level university course on VLSI testing. The student is presumed to have only basic understanding of logic circuits and introductory ideas of VLSI technology. This set of five lectures includes simple classroom exercises and discussion on theoretical and practical aspects of VLSI testing. The objective is to fulfill the needs of today’s industrial VLSI design and manufacturing environment, which demands knowledge of testing concepts.

The presentation material is based on the textbook, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000.

Syllabus:

  1. Fault Modeling (stuck-at and other faults)
  2. Logic Simulation (modeling levels, event-driven simulation)
  3. Fault Simulation (parallel, deductive and concurrent methods)
  4. Combinational Circuit Test Generation (D-algorithm, Podem)
  5. Sequential Circuit Test Generation (time-frame, simulation-based)