Program

Download the complete course description as pdf.

Saturday, May 22

08:00
Welcome Address
Hans-Joachim Wunderlich

08:15
Basics on VLSI Technology in Test
Adit Singh

14:00
Fault Models, Fault Simulation and Test Generation
Vishwani Agrawal

18:30
Dinner

Sunday, May 23

08:00
Defect Based Testing and Diagnosis
Michel Renovell

14:00
Design for Test, BIST and BISR
Jerzy Tyszer

18:30
Dinner

Monday, May 24

08:00
Reliability and Design for Manufacturing
Abhijit Chatterjee

14:00
Infrastructure IP for SOC
Yervant Zorian

14:00
Test of TSV-based 3D Stacked ICs
Erik Jan Marinissen