Basics on VLSI Technology in Test

Lecture

May 22 08:15
Mariapoli

Adit Singh
Auburn University

The testing of complex integrated circuits is extremely challenging because of the exponential nature of the problem; applying all possible input combinations to fully check a large circuit can require test time of the order of centuries, even at the fasted possible clock rates. In practice, only tiny fraction of the input space can be tested in reasonable time and cost. But such a limited test must still ensure that virtually all defects in the circuit are detected so as to avoid failure during operation. This requires careful selection of the test inputs to ensure that they target all the likely circuit faults. Fortunately not all possible functional failures in a circuit are equally likely, and many are virtually impossible, making it practical to achieve high test quality without applying all possible inputs.

Targeting likely circuit faults requires an understanding of the underlying circuit structures and manufacturing technologies, and the possible sources of manufacturing and field failures. This introductory session will review the basics of CMOS technology, before moving on to discuss the types and sources of common manufacturing defects and their impact on circuit performance. Tests to detect specific types of circuit faults will be introduced. Following discussion of the traditional stuck-at, bridging, IDDQ, and transition delay test approaches, challenges posed by state-of-the-art nanometer technologies such as latent faults, small delay defects, and random performance variability will also be presented.

Syllabus:

  1. Introduction
  2. The evolution of IC technologies
  3. CMOS circuit structures
  4. Overview of CMOS processing
  5. Technology scaling and advanced materials
  6. Manufacturing defects and the yield challenge
  7. The importance of testing to ensure product quality
  8. The exponential complexity of test
  9. Reducing test set size by targeting logical faults
  10. The stuck-at-fault model
  11. How good is the stuck-at fault assumption?
  12. CMOS physical defects modeled with stuck open and bridging faults
  13. IDDQ testing
  14. Delay and timing defects and fault models
  15. Process variability
  16. Latent defects and the need for stress testing
  17. Summary
  18. Conclusion and discussion