|
Lecture May 23 14:00 |
The rapid scaling of semiconductor devices along with technological innovations allow designers to embed more than 100 million transistors running in the GHz range. Testing designs of this complexity is a significant challenge.
This lecture will focus on some of the advances shaping the test industry to address design and process changes. In particular, we will present state-of-the-art design-for-test (DFT) methodologies and practices for high-quality low-cost manufacturing test. In addition to scan-based testing and issues related to at-speed testing in scan environment, the lecture will cover guidelines for design of built-in self-testable cores, techniques for random pattern testability, as well as BIST architectures for random logic and memory arrays, including built-in self-repair (BISR) schemes. The lecture will also highlight, from a DFT perspective, methods deployed both to control test power dissipation and to reduce a negative impact of unknown states on test quality. Finally, we will illustrate applications and discus future trends of DFT technology.
Syllabus:
- Introduction
Testing of sequential circuits, functional and random tests, sequential ATPG, test time - Why DFT?
Logic-to-pin ratio, circuit complexity, test generation time, volume of test data, performance testing, state variables, controllability and observability, ability to set internal nodes and to propagate their values to outputs, measures of circuit testability, ad hoc DFT techniques - Scan-based designs
Scan cells, multiplexing of data flip-flops, impact on performance, modes of operation, generic scan path, parallel scan chains, test application time, safe scan shifting, testing procedure, flush test, scan shift and capture operations, partial scan - Test points
Observation and control points, selection of test points, test points driven by scan, multiphase test point insertion - Benefits and cost of scan
Impact on controllability, observability, testability, ATPG, and fault simulation, hardware debugging and verification, fault diagnosis, area overhead, performance degradation, scan test cost - Low power scan-based test
Reducing power dissipation, solutions for scan testing in shift and capture, test scheduling and reordering, scan partitioning, transition blocking, clock gating, low-transition test pattern generators, minimum transition fill, patterns with low switching activity, low power scan operations - Level sensitive scan design (LSSD)
Hazard-free latches, design rules, double-latch design, single-latch design - Boundary scan
Objectives, boundary scan architecture, standard IEEE 1194.1, TAP state diagram, board testing, testing of interconnects, invoking BIST functionality - At-speed scan-based test
Single clock domain - single capture, over-testing, speed of loading, timing in capture window, frequency to reduce power and constraints on BIST controller, frequency to reduce test time, double capture, launch from a semi-legal state, slow scan enable, multiple clock domains, at-speed testing within and between clock domains, clock suppression, hold states, multiple frequencies - single capture - Built-in self-test (BIST)
External testers, tester accuracy, capacity and bandwidth, test application time, cost, volume of test data, yield loss due to ATE inaccuracy, BIST principles, on chip test generation and response evaluation, devices to produce test patterns and compact test responses, BIST-ready designs, BIST-ready designs with scan, STUMPS architecture, pseudo-random testing, fault coverage by random patterns - On-chip test pattern generators
Generation of pseudorandom test patterns, test sequence aperiodicity, structural and linear dependencies, driving large number of scan chains, operational speeds, linear feedback shift registers (LFSRs), primitive characteristic polynomials, m-sequence, principle of superposition, hybrid LFSR and cellular automata, ring generators, two-dimensional generators, phase shifter synthesis, weighted pseudo-random patterns, low transition PRPG -
Test data volume compression
Stimuli replication, stimuli encoding, static reseeding of LFSRs, solving of linear equations, compression ratios and encoding efficiency, multiple polynomial reseeding, continuous flow decompression (dynamic reseeding), embedded deterministic test, low power decompression, merging of incompatible test cubes - Compaction of test responses
Objectives, placement of compactor, properties of ideal compactors, time compactors (signature analysis, arithmetic accumulation, counting), space compactors (XOR trees, error code-based), finite memory compactors, error models and aliasing, aliasing probability, Markov model, transient period - Multiple input signature register (MISR)
Parallel data acquisition, multiple error injections, unknown (X) states and their sources, X states and signatures, X-masking schemes, X-bounding logic - Compaction and diagnosis
Bypass mode, scan partitioning for diagnosis, identification of failing scan cells - Built-in logic block observer (BILBO)
- BIST controller
Architecture, BIST session, logic BIST flow, parameters defined from BIST-ready process, user defined options, determined by synthesis tools, boundary scan and BIST - Arithmetic and software BIST
- Memory BIST
Requirements, fault models, choice of algorithms, types of memories, RTL insertion, configurations, operating speed, data retention, data backgrounds for word memories, parallel memory BIST, serial memory BIST, serial-parallel data interface trade-offs, memory BIST collar, shared controller and parallel test, parallel memory BIST collar, programmable algorithms, fault diagnosis for RAMs and ROMs - Built-in self-repair