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Lecture May 24 08:00 |
CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as the associated signal processing algorithms for real-time systems must be designed for worst case operating conditions (e.g. environmental noise). This forces designers to excessively guard band their circuits while using "aggressive" back-end algorithms to support the end application, resulting in unacceptable power-performance-yield tradeoffs. One way to tackle this problem is to design circuits and relevant signal processing algorithms that are “aware” of their environmental operating conditions and manufacturing process conditions and use this “self-awareness” to perform adaptation that conserve power while maximizing yield and reliability. Such self-adaptation involves incorporation of built-in test, diagnosis and tuning/adaptation mechanisms into the circuits and systems concerned. A key issue is that of test, diagnosis and tuning of complex circuit and system-level parameters that must be evaluated and traded off against one another during the adaptation process without access to complex external test instrumentation. This talk summarizes recent results obtained in the design of such highly reliable and manufacturable (in the face of process uncertainties) computing and communication systems and points to directions for future work in this area.
Syllabus:
- Definition of testing problem:
- digital vs. analog testing
- fault based vs. spec based
- test flow for ICs
- test flow for packages
- what are we testing for?
- Reliability models:
- electromigration
- hot carrier effects
- reliability of deeply scaled devices, NBTI
- temperature effects and wearout
- digital vs. analog
- system level reliability and mean time to failure
- Design for manufacturability:
- rule based design
- optical proximity correction
- tuning techniques
- Introduction to Systems-on-Chip (SoCs):
- test problems
- test access techniques
- IEEE P1500 standard
- Contemporary spec based testing of analog and RF modules:
- opamps
- data converters
- regulators
- SerDes devices
- RF modules and systems
- common instruments used: rack and stack systems
- common tests performed
- spec test optimization methods
- Fault modeling for analog and RF modules:
- top down vs. bottom up modeling
- catastrophic and parametric fault modeling
- guardbanding and setting test limits
- coverage models for analog
- The alternate testing paradigm:
- Core concepts
- test generation
- test methodology in production test
- Application to precision opamps (industrial test case)
- Application to CDMA LNA devices
- Process diagnosis
- System level alternate test and BIST:
- Low cost testing of GSM transceiver
- Low cost testing of OFDM transceiver
- BIST using embedded sensors
- BIST for nonlinearity, mismatch and EVM
- Self-calibration techniques and adaptive systems:
- one-shot tuning using alternate diagnostic tests
- iterative test driven LMS based tuning
- transmitter and receiver tuning against complex specs (EVM)
- autonomous adaptation to process and environment
- Self-test techniques for SoCs:
- loopback testing of ADC and DAC modules
- predicting individual parameters from loopback tests
- spectral techniques applied to loopback test
- on-chip sensors for low-cost test of RF modules
- prototype hardware and chip measurement results
- directions for self-adapting SoCs
- Directions for future research:
- error detection and fault tolerance
- self aware systems