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Lecture May 23 08:00 |
Opens and Shorts defects are responsible for a large percentage of failures in CMOS technologies and their impact in nanometer technologies with highly dense interconnect structures is expected to increase. In this presentation a survey of the key developments in modelling open and short defects as well as floating gate and gate oxide short and their implications in test and diagnosis are presented. An overview of the historical developments of these models to more realistic proposals taking into consideration the unpredictable parameters of the defect such as resistance, location, etc are presented. The logic detectability of defects taking into consideration their unpredictable parameters assuring their detectability is explored. The concept of Analogue Detectability Interval (ADI) as well as its applicability to increase the quality of the vectors detecting these defect classes is introduced. Quality of electronic circuits and systems requires the availability of effective diagnosis techniques. The basic concepts of logic as well as current-based (IDDQ) diagnostic strategies are included in this presentation.
Syllabus:
- Test with Classical Fault Models
- Stuck-at
- Wired-OR
- Wired-AND
- Dominant
- Stuck-Open
- Diagnosis with Classical Fault Models
- Stuck-at
- Wired
- Realistic Fault Models
- Voting
- Biased Voting
- Direct Voting
- Analysis of Realistic Defects
- Resistive short
- Resistive Open
- Floating gate
- Gate Oxide Short
- Diagnosis with Realistic Defects
- Test with Realistic Defect Models
- Detection Interval
- Global Detection Interval
- Efficiency metrics