Test of TSV-based 3D Stacked ICs

Lecture

May 24 14:00
Track B

The semiconductor industry is preparing itself for three-dimensional stacked integrated circuits (3D-SICs) based on Through-Silicon Vias (TSVs). TSVs are conducting nails which extend out of the back-side of a thinned-down die and enable the vertical interconnection to another die. TSVs are high-density, low-capacity interconnects compared to traditional wire-bonds, and hence allow for many more interconnections between dies, while operating at higher speeds and consuming less power. TSV-based 3D technologies enable the creation of a new generation of ‘super chips’ by opening up new architectural opportunities, allowing mixing of heterogeneous process technologies, at a smaller footprint and lower manufacturing cost. Due to their many compelling benefits, 3D-SIC technology is quickly gaining ground, and hence might help the semiconductor industry to extend the momentum of Moore’s Law into the next decade.

Testing for manufacturing defects is considered by many as a major, still largely unresolved obstacle to make 3D integrated circuits a reality. There are concerns about testing cost, and even the feasibility of testing such TSV-based 3D-SICs.

However, the test community is waking up to address these challenges, testifying to the fact that 3D-SICs soon will hit the markets.

In this presentation, after a review of TSV-based technologies, we present a structured overview of the challenges in testing 3D-SICs, along with solutions as far as available today. Whereas these ‘super chips’ require most of today’s advanced test and DfT approaches, they also have some unique challenges of their own. These include:

  1. development of new fault models and corresponding tests for thinned-die defects and TSV-based interconnects
  2. wafer probing on small and numerous micro-bumps and/or TSV tips under stringent damage requirements,
  3. handling of and probing on wafers with thinned-die stacks,
  4. further strengthening of the well-known modular test concept,
  5. the design, partitioning, and optimization of DfT architectures that span across multiple dies,
  6. optimization of the test flow for maximum effectiveness and lowest cost.

Syllabus:

  1. Introduction
  2. 3D Stacked ICs
    • Motivation
    • Application drivers
    • 3D manufacturing steps (incl. TSV formation, wafer thinning, and bonding)
    • Manufacturing options
  3. 3D Test Flows
    • Wafer test and final test; pre-bond and post-bond testing; KGD and KGS testing
    • The value of pre-bond testing in W2W stacking
  4. Modular Testing
    • Motivation for modular testing for 3D-SICs
    • Infrastructure for modular testing
  5. 3D Test Contents
    • Tests for new intra-die defects
    • Tests for TSV-based interconnects
  6. 3D Wafer Test Access
    • Challenges and solutions for pre-bond die testing
    • Challenges and solutions for post-bond stack testing
  7. 3D DfT Architectures
    • Basic DfT architecture
    • The role of RPCT, TDC, and BIST
  8. Conclusion
    • Tutorial summary
    • Evaluation with / by audience