Technology Trends in VLSI and Impact on Reliability and Test

Lecture

May 21 10:30
Nidaros Pilgrim Centre


Shekhar Borkar
Intel Corporation

As technology continues to scale in the nanoscale regime, it's the same physics that helped you in the past, now poses major challenges in design, reliability, and test. Future designs will have to comprehend them, and incorporate reliability and test into the design from day one. Traditional system level reliability techniques will be ill suited and will have to morph towards resiliency. This course will address all of these challenges.

Prerequisites

Fundamental knowledge of physics, electronics, and electrical engineering at the undergraduate level is required.

Suggested preliminary readings

  • Jan Rabaey: Low Power Design Essentials, Springer, ISBN 1558-9412
  • Neil Weste and David Harris: CMOS VLSI Design, A Circuit and System Perspective, Third Edition and Addison Wesley, ISBN 0-321-14901-7
  • James Segura and Charles F. Hawkins: CMOS Electronics, How it works, how it fails, IEEE Press, ISBN 0-471-47669-2

Learning outcomes

This course will familiarize you with the challenges of the nanoscale technologies, and effective design practices to overcome these challenges, both at the chip level as well as at the system level. You will be equipped with a good understanding of how to incorporate test and reliability into the design from day one, and to look forward to the paradigm shifts of resilient design for even more effective designs.

Syllabus

  1. Nanoscale Technologies: We will discuss the evolution of MOS transistors from yesterday's micro-scale to today's nanoscale regime, physics behind the scaling, and the same physics that now pose challenges for the future scaling. This includes subthreshold leakage, gate leakage, random and systematic variations, their causes, and the impact on VLSI chips.
  2. VLSI Design Challenges of Nanoscale Technologies: We will discuss challenges associate with designing logic and circuits, considering major technological shifts discussed before. This includes design considerations for static, sequential, and storage circuit elements, with power management and delivery. We will further discuss the causes of faults, such as device aging, electromigration, as well as intermittent faults such as single event upsets, the errors caused by them, and design considerations to work around. We will especially focus on the reliability and test aspects from the design point of view.
  3. System Design Challenges: Building systems with these components will be challenging too. System on a chip, as well as traditional board level system design will have to follow different design philosophy. We will discuss challenges associated at the system level, to provide sufficient IO bandwidth, power delivery and management, system reliability, and test - all within a reasonable power and cost envelope.
  4. Designing for Reliability and Test: Having discussed the technological and design challenges we will focus on reliability and test aspects of the system. Traditional testing of components - as an afterthought - will be ineffective, and the future designs will have to incorporate testing as an integral part of the design effort. Traditional reliability solutions at the system level - such as N modular redundancy - too needs overhaul to morph into a new paradigm of system resiliency. We will discuss how designing for resiliency, with test and reliability in mind, will result in robust, reliable, and high yielding systems.