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Lecture May 23 14:00 |
Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of device-parameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality.
The objective of this course is to provide PhD and MSc students with an overview of fault modeling and test design for memory devices. Traditional fault modeling and recent development in fault models for current and future technologies are covered. Systematic methods for designing and optimizing test patterns are presented, and supported by industrial results. Memory Built-In-Self Test, as a common industrial method to implement the test algorithms, is discussed. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.
- Prerequisites & suggested preliminary readings
It is recommended to read about the semiconductor memory architectures; especially SRAMs and DRAMs. The main blocks (e.g., address decoders, the memory cell array, etc) forming a memory system and how the operations (i.e., read and write) are performed should be known and understood. Any paper or book covering the functionality of semiconductor memories can provide this basic knowledge.
- Learning outcomes
Upon the completion of the course, the attendee will:
- have a good knowledge of practices in memory testing,
- understand the major types of memory faults,
- know which tests should be performed to target each fault class,
- have a feeling of the effectiveness of each test,
- have the capability to develop new tests for any observed new faulty behavior and optimize them for specific application,
- understand how to design a Memory BIST,
- choose appropriate test strategy to achieve a high fault coverage with the minimum cost, and
- get insight into the direction and future of memory testing.
- Syllabus
- Motivation
- Quality versus reliability
- Importance of (memory) testing
- Memory Fault Models
- Traditional fault models
- Advanced fault models
- Test Algorithms
- Traditional tests
- March tests
- Fault-primitive based tests
- Industrial Test Results
- Memory Built-in-Self Test (MBIST)
- MBIST requirements
- Traditional MBIST architectures
- Advanced MBIST architectures
- Future challenges