TU Delft, The Netherlands
My current scientific research focuses on quantum computing and more specifically on the definition and implementation of a scalable quantum micro- and system architecture. This involves specifying what the micro-architectural support is for the control of the quantum instructions and how the quantum accelerator is connected and integrated in a larger system design where classical logic is combined with quantum logic. There are two dimensions that are being followed: the first is to define and develop the micro- architecture for the experimental quantum chip. This work is basically done, and we need to expect a higher number of qubits. The second dimension wants to focus more on quantum accelerators and how they can be implemented in any quantum accelerator technology. That work is based on the full-stack definition that the QCA lab has defined and developed. In this context, we have defined a programming language, OpenQL, a template for the micro-architecture and the QX simulator platform to execute any quantum logic that can be defined. I personally am no longer involved in the Intel project as the main challenges for the architecture group have been solved. In that context, I am looking at two different quantum accelerator applications and will construct a company, called QuantumForce, to work on the implementations. There is potential collaboration with a German car manufacturer and the Lawrence Berkeley National Laboratory on two different topics. More specifically, we are studying the challenges of mapping a quantum circuit on a 2D qubit plane and what qubit state routing is needed. To this purpose, we assess to what extent the current, classical NoC algorithms can be modified such that it is useful for any particular 2D quantum chip. We are also building a large-scale simulation model for a very elaborate study of the micro-architecture assuming a very large number of qubits. Evidently, we need to expand the OpenQL language such that any logic can be implemented and tested. In the past, I was involved in electronic system level design aiming at supporting the entire design process of both software and hardware components for heterogeneous multi-core platforms. I started the Delft Workbench project which ultimately led to the largest FP6 project ever funded (hArtes) resulting in a hardware abstraction layer and corresponding tool set such that existing or new applications can be ported to any kind of heterogeneous hardware platform. This line of research is now also increasingly relevant for Big Data applications and emerging high-performance computing platforms from IBM, Convey and Intel. I started multiple companies, one of which is a spin-off, BlueBee, that applies these technologies in a cloud-service for genome sequencing.
7 books as editor, 37 journal publications and more than 160 peer reviewed conference papers. 30 PhD students graduated with me and I currently supervise 3 students. Organisation of 11 international workshops and conferences as program or general chair. Started 5 companies in various fields. Citation index is 27.
Alberto Bosio, Ecole Centrale de Lyon, France
Alberto Bosio received the Ph.D. in Computer Engineering from the Politecnico di Torino, Italy in 2006. From 2007 to 2018 he was an Associate Professor at LIRMM - University of Montpellier in France. From September 2018 he joined the INL u2013 Ecole Centrale de Lyon, France as Full Professor. His research interests include Approximate Computing, In-Memory Computing, Test and Diagnosis of Digital circuits and Reliability Assessment.
Summary of the hot points:
Co-author of 1 book and 1 book-chapter, 4 patents, 42 papers in international journals and more than 130 papers in international conferences and workshops (the full and updated list is available at http://perso.ec-lyon.fr/alberto.bosio/).
12 invited papers in international conferences.
4 Embedded Tutorials.
Co-supervisor of 15 Ph.D. students.
Co-supervisor of 3 PostDoc students.
Supervisor of more than 30 master students.
Participation to overall 15 european- and national-funded projects and research contracts with industrial partners (since 2006)
Program Chair of DTIS 2018, DDECS 2019, DDECS 2020, AxC19
Review Chair of DATE 2018, DATE 2019, ETS 2015, ETS 2016
Publication Chair of SIESu201908, DTISu201915, DTISu201916, DTISu201917, ETSu201915, ETSu201916, ETSu201917
General Chair of AxC Workshop 2018, South European Test Seminar (SETS 2014)
u201cTesting, Reliability, and Fault-Toleranceu201d Track Chair of ISVLSIu201915, ISVLSIu201916 and ISVLSIu201917
Topic Chair of DDECSu201916, ETSu201919, ETSu201920
Associate Editor of Journal of Circuits, Systems and Computers ( https://www.worldscientific.com/worldscinet/jcsc )
Guest Editor of Microelectronics Reliability ( https://www.journals.elsevier.com/microelectronics-reliability )
Reviewer for French and European projects
Electronic Media chair of u201cTest Technology Technical Council (TTTC)u201d (tab.computer.org/tttc) of IEEE Computer Society (from 2012)
Electronic Media chair of u201cTest Technology Educational Program (TTEP)u201d ( http://ttep.tttc-events.org/ttep/index.html ) of IEEE Computer Society (from 2012)
Member of the program committee of several international conferences and reviewers for several journals
Best paper awards at DDECSu201916, ICMu201915,VALIDu201909
Paper selected to be published in the post-conference book of VLSI-SOC 2016.
Best Special Session award at VTSu201916
European Test Technology Technical Council (ETTTC) chair from 2018
Duke University, USA
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the John Cocke Distinguished Professor and Department Chair of Electrical and Computer Engineering, and Professor of Computer Science, at Duke University.
Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), multiple IBM Faculty Awards and HP Labs Open Innovation Research Awards, and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), the Semiconductor Research Corporation Technical Excellence Award (2018), and the IEEE Test Technology Technical Council Bob Madge Innovation Award (2018). He is a Research Ambassador of the University of Bremen (Germany) and a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany. He is a 2018 recipient of the Japan Society for the Promotion of Science (JSPS) Fellowship in the Short Term S: Nobel Prize Level category.
Prof. Chakrabartys current research projects include: testing and design-for-testability of integrated circuits and systems; microfluidic biochips; hardware security; machine learning for fault diagnosis and failure prediction; neuromorphic computing systems. He is a Fellow of ACM, a Fellow of IEEE, a Fellow of AAAS, and a Golden Core Member of the IEEE Computer Society. He was a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010- 2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012- 2013), and an ACM Distinguished Speaker (2008-2016). Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design, Test of Computers during 2010-2012, ACM Journal on Emerging Technologies in Computing Systems during 2010-2015, and IEEE Transactions on VLSI Systems during 2015-2018.
University of Utah, Salt Lake City, USA
Priyank Kalla is a Professor in the Electrical & Computer Engineering department at the University of Utah. He received the B.E. degree in Electronics Engineering from Sardar Patel University (India) in 1993, and M.S. and Ph.D. from the Univ. of Massachusetts Amherst (USA) in 1998 and 2002, respectively. Prior to joining the University of Utah in 2002, he worked with AMD K-7 RTL design team, Cadence Design Systems Synergy Logic Synthesis team, and the Digital Equipment Corp. DEC Alpha microprocessor CAD & Test group. His areas of interests are in design automation for VLSI and post-CMOS VLSI systems, and in formal hardware verification. The focus of his current research projects is on: i) design, automation and validation of silicon-based integrated optic systems; and ii) formal verification, debug and rectification of arithmetic circuits using computational algebraic geometry.
He is a recipient of the US National Science Foundations Faculty Early Career Development (CAREER) award (2006) and 3 best paper awards, including the ACM Trans. on Design Automation best paper award (2009). He was the chair of IEEE technical committee on computer-aided network design (CANDE) and has also served as an associate editor for IEEE Trans. on CAD.
Purdue University, USA
Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain- inspired computing (C-BRIC) funded by SRC/DARPA. His research interests include neuromorphic and emerging computing models, neuro-mimetic devices, spintronics, device-circuit-algorithm co-design for nano-scale Silicon and non-Silicon technologies, and low-power electronics.
Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (Charles Desoer Award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
Mehdi Tahoori is a full professor and Chair of Dependable Nano-Computing (CDNC) at the Institute of Computer Science & Engineering (ITEC), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He received his PhD and M.S. degrees in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and a B.S. in Computer Engineering from Sharif University of Technology in Iran, in 2000. In 2003, he joined the Electrical and Computer Engineering Department at the Northeastern University as an assistant professor where he promoted to the rank of associate professor with tenure in 2009. From August to December 2015, he was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA, in the area of advanced computer-aided research, engaged in reliability issues in deep-submicrometer mixed-signal very large-scale integration (VLSI) designs.
He holds several pending and granted U.S. and international patents. He has authored over 250 publications in major journals and conference proceedings on a wide range of topics, from dependable computing and emerging nanotechnologies to system biology. His current research interests include nanocomputing, reliable computing, VLSI testing, reconfigurable computing, emerging nanotechnologies, and systems biology. Prof. Tahoori was a recipient of the National Science Foundation Early Faculty Development (CAREER) Award. He has bee a program committee member, organizing committee member, track and topic chair, as well as workshop, panel, and special session organizer of various conferences and symposia in the areas of VLSI design automation, testing, reliability, and emerging nanotechnologies, such as ITC, VTS, DAC, ICCAD, DATE, ETS, ICCD, ASP-DAC, GLSVLSI, and VLSI Design. He is currently an associate editor for IEEE Design and Test Magazine (D&T), coordinating editor for Springer Journal of Electronic Testing (JETTA), associate editor of VLSI Integration Journal, and associate editor of IET Computers and Digital Techniques. He was an associate editor of ACM Journal of Emerging Technologies for Computing. He received a number of best paper nominations and awards at various conferences and journals, including ICCAD 2015 and TODAES 2017. He is the Chair of the ACM SIGDA Technical Committee on Test and Reliability.
TSS Co-Chair, Sorbonne University, LIP6, France
Hamburg University of Technology, Germany
KU Leuven, Belgium
Tallinn University of Technology, Estonia
Tallinn University of Technology, Estonia
Tallinn University of Technology, Estonia
Tallinn University of Technology, Estonia
Jan Dennis Reimer
University of Paderborn, Germany