Janusz Rajski

Janusz Rajski

Mentor, A Siemens Business

8005 S.W. Boeckman Rd
Wilsonville
OR 97070
USA

Biography

Janusz Rajski, vice president of Engineering, Tessent, joined Mentor, A Siemens Business in 1995 as chief scientist and in 2002 became engineering director of the Tessent product line. During his tenure at Mentor he has built a strong R&D organization with focus on innovative Design for Test technologies and collaboration with leading semiconductor companies. Under his leadership the team has developed a number of revolutionary industry-first products: TestKompress, the first commercial test compression product, and Cell-Aware Test technology which provides unprecedented test quality and accuracy of diagnosis. Both are increasingly important for smaller technology nodes and automotive applications. Innovations such as these have brought Mentor’s Design for Test business to its number one position in the industry.

Prior to joining Mentor, he was a faculty member with the Poznań University of Technology. In 1984, he joined McGill University, Montréal, Canada, where he became an associate professor in 1989. He has published more than 240 IEEE research papers and is co-inventor of more than 120 US and international patents. His papers and patents have over 12,000 citations and won many prestigious awards.

An IEEE Fellow, he holds a Master of Science degree in electrical engineering from the Gdańsk University of Technology and a Ph.D. degree in electrical engineering as well as an honorary doctorate from the Poznań University of Technology. In 2003, he was awarded the prestigious title of “Professor of Science” by the President of Poland.

Harry Chen

Harry Chen

MScientist, IC Testing at MediaTek

Biography

Harry Chen is currently IC Testing Scientist at MediaTek in Taiwan. He is also a senior staff member involved in strategic technology assessment, planning, and external research collaboration. His interests in testing include defect modeling, adaptive test, and system-level test (SLT). He actively participates in test-related conferences such as ITC, ATS, ETS, VTS, and VLSI-DAT by serving on program committees, publishing papers, and giving talks. His recent papers and patents address the topics of test data analytics and cell-aware defect modeling (received Best Paper of ATS 2016). He also participates in the international Heterogeneous Integration Roadmap collaboration effort by leading the task to define the future direction of SLT under the Test Roadmap Team. Prior to MediaTek, Harry worked in the USA at Analog Devices where he was responsible for chip integration and implementation flow of multiple wireless baseband products. And before ADI, Harry led and managed the development of test automation tools at Cadence Design Systems. Harry attended graduate school at Stanford University where he did doctoral research on VLSI testing and received an MSEE. His undergraduate degrees are in Biology and EE, both received from MIT.

Rolf Drechsler

Rolf Drechsler

University of Bremen/DFKI Bremen

Bibliothekstr.5
28359 Bremen
Germany

 Email:

 Web: www.informatik.uni-bremen.de/agra  - http://www.rolfdrechsler.de/

 Twitter: @Rolf_Drechsler

 Phone: +49 421 218 63932

Biography

Rolf Drechsler (http://www.rolfdrechsler.de/) received the Diploma and Dr. phil. nat. degrees in computer science from the Johann Wolfgang Goethe University in Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He worked at the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and at the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001.

Since October 2001, Rolf Drechsler is Full Professor and Head of the Group of Computer Architecture, Institute of Computer Science, at the University of Bremen, Germany. In 2011, he additionally became the Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an IEEE Fellow.

Rolf Drechsler was a member of Program Committees of numerous conferences including e.g., DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, and FMCAD. He was Symposiums Chair at ISMVL 1999 and 2014, and the Topic Chair for "Formal Verification" at DATE 2004, DATE 2005, DAC 2010, and DAC 2011. He is a co-founder of the Graduate School of Embedded Systems and he is the coordinator of the Graduate School "System Design" funded within the German Excellence Initiative. He received best paper awards at the Haifa Verification Conference (HVC) in 2006, the Forum on specification & Design Languages (FDL) in 2007 and 2010, the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in 2010 and the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2013.

Rolf Drechsler is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, IET Cyber-Physical Systems: Theory & Applications, International Journal on Multiple-Valued Logic and Soft Computing, and ACM Journal on Emerging Technologies in Computing Systems.

Haralampos-G. Stratigopoulos

Haralampos-G. Stratigopoulos

Sorbonne Université, CNRS, LIP6

Paris, France

Biography

Haralampos-G. Stratigopoulos received the Diploma in electrical and computer engineering from the National Technical University of Athens, Greece, in 2001 and the Ph.D. in electrical engineering from Yale University, USA, in 2006. From October 2007 to May 2015 he was a Researcher with the French National Center for Scientific Research (CNRS) at TIMA Laboratory, Université Grenoble Alpes, Grenoble, France. Currently he is a Researcher with the CNRS at LIP6 Laboratory, Sorbonne Université, Paris, France. His main research interests are in the areas of design-for-test and built-in self-test for analog, mixed-signal, RF circuits and systems, computer-aided design, machine learning applications in manufacturing and test, and hardware security. He was the General Chair of the 2015 IEEE International Mixed-Signal Testing Workshop (IMSTW) and the Program Chair of the 2017 IEEE European Test Symposium (ETS). He has served on the Technical Program Committees of Design, Automation, and Test in Europe Conference (DATE), IEEE International Conference on Computer-Aided Design (ICCAD), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE International Test Conference (ITC) and several others international conferences. He has served as an Associate Editor of Springer Journal of Electronic Testing: Theory & Applications, IEEE Design & Test Magazine, and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He received the Best Paper Award in the 2009, 2012, and 2015 IEEE European Test Symposium (ETS).

Peter Maxwell

Peter Maxwell

ON Semiconductor

 Email:

Biography

Peter Maxwell works for ON Semiconductor, where he is responsible for test and DFT for CMOS image sensors. He received the B.Sc. and M.Sc. degrees in Physics from the University of Auckland, New Zealand, and the Ph.D. degree in Electrical Engineering and Computer Science from the Australian National University.  He is a Fellow of the IEEE.

His interests include test methodologies, design for testability, and their application for yield improvement, diagnosis, quality and test time reduction. He spent many years coordinating test experiments and was one of the first to widely publish industrial data on test effectiveness. He has been involved on the organization and program committees of numerous conferences, including Program Chair of the VLSI Test Symposium and the International Test Conference.

Jeff Rearick

Jeff Rearick

AMD Senior Fellow

 Email:

Biography

Jeff Rearick is a Senior Fellow at Advanced Micro Devices, where he and his team are responsible for the Design-For-Testability strategy and roadmap for the company. In his 12 years at AMD, and in the 22 previous years which Jeff spent at HP/Agilent, he has worked on many aspects of integrated circuit testing, from hands-on testing of microprocessors to test automation tools to DFT architecture, including the design and use of on-chip instruments for testing complex digital functions and analog/mixed-signal circuits like high-speed I/Os and delay-locked loops.

Jeff extended his embedded test work by co-founding the IJTAG Working Group, whose efforts became standardized in 2014 as IEEE 1687 (Access and Control of Instrumentation Embedded within a Semiconductor Device), for which Jeff served as the Editor. In recognition of the impact of that work, he received the 2016 Bob Madge Innovation Award at the International Test Conference, as well as the 2018 IEEE Hans Karlsson Award. He built on that momentum by co-founding three currently active working groups: IEEE P1687.1 for the re-use of functional interfaces and controllers to access 1687 networks, IEEE P1687.2 for describing analog test access and control (for which he is again serving as Editor), and IEEE P2427 for analog defect coverage measurement. Jeff has also received a Special Recognition Award for his efforts in the development and first silicon demonstration of IEEE 1149.6 (AC Boundary Scan) and a Certificate of Appreciation for his role in IEEE 1804 (Fault Coverage and Accounting). He is a longstanding member of the IEEE Test Technology Standards Committee.

In addition to his standards work, Jeff has served on the Program Committee of the International Test Conference for 10 years and has contributed to the Program Committee of the European Test Symposium. He holds over 40 U.S. patents and has presented dozens of technical papers, invited addresses, and keynotes at various conferences. Jeff earned BSEE and MSEE degrees from Purdue University and the University of Illinois, respectively.

Lorena Anghel

Lorena Anghel

TIMA Grenoble

46, avenue Felix Viallet
Grenoble, 38031
France

 Email:

Sybille Hellebrand

Sybille Hellebrand

Universität Paderborn

 Email:

Mehdi Tahoori

Mehdi Tahoori

Karlsruhe Institute of Technology
 Email:

Artur Jutman

Artur Jutman

Tallinn University of Technology

Jaan Raik

Jaan Raik

Tallinn University of Technology

Görschwin Fey

Görschwin Fey

Hamburg University of Technology

Iris Schröder-Piepka
Iris Schröder-Piepka

Karlsruhe Institute of Technology
 Email:

Dennis Rolf Engelbert Gnad
Dennis Rolf Engelbert Gnad

Karlsruhe Institute of Technology
 Email: