This class looks at the challenges of ensuring dependability and resilience in emerging systems and technologies,
which include FinFETs and subsequent extensions such as gate-all-around device, as well as emerging memories such as
STT-MRAM and various resistive RAMs. Participants will learn the components of dependability and will see how these
interact with design components in order to build robust systems. Problems will be approached from their base technology
drivers, showing their impact on design. In addition, we will look top down, from market and application needs,
and show how resilience and dependability drive design and technology.
- Introduction and background
- Class goal
- What is resilience?
- Why is it important?
- Quality, safety, dependability, and reliability
- Components of resilience
- Variability
- Soft errors
- Aging
- Power integrity
- Random Telegraph Noise
- Overview of emerging technologies
- FinFET
- Gate-all-around
- Tunnel FETs
- Nanowires, nanotubes, spintronics, and qubits
- Classic memories: SRAM, DRAM, Flash
- MRAM
- ReRAM
- MEMS
- Design techniques for resiliency
- Basics of CPU design
- Triple-modular redundancy
- Lock-step operation
- Basics of memory design and margining
- Redundancy and repair
- Error-correcting codes
- Razor
- Soft-error tolerance
- Interaction of resiliences with margins
- Resilience and test
- Defects and faults
- Static test
- Timing test
- Burn-in
- Market requirements for resiliency
- The semiconductor business by process node, market, and application
- Costs of resiliency
- Resiliency standards
- Conclusions and future directions
Basic VLSI design, circuit design
Attendees will learn the basics of resilient design practice for circuits and CPU-centric systems.
Emphasis is placed on practical application over theoretical background, although the latter is provided where needed.
