Vertical die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration,
inter-die interconnect density, performance, and energy efficiency, and component size and yield. The creation of system chips
consisting of multiple stacked dies is enabled by the ability to manufacture dense arrays of small micro-bumps and through-silicon
vias (TSVs), along with technologies like wafer thinning, back-side processing, and temporary and permanent bonding of dies and wafers.
We distinguish between 2.5D- and 3D-stacked integrated circuits: in 2.5D-SICs, multiple active dies are placed side-by-side on top of
and interconnected by a passive interposer die; in 3D-SICs, multiple active dies are stacked on top of each other. Both types of SICs
serve their particular market segments and are here to stay; 2.5D-SICs provide better chip cooling options and hence typically target
high-performance computing and networking applications, whereas 3D-SICs with their small footprint are better suited for mobile
applications.
Like all ICs, also these new SICs need to be tested for manufacturing defects, in order to guarantee sufficient outgoing product
quality to the customer. SICs typically contain complex circuits in advanced technology nodes, and hence require most of today’s advanced
test and DfT approaches. However, they also have some unique test challenges of their own, related to (1) optimizing test flows,
(2) test contents, and (3) test access.
In this lecture, after an introduction of 2.5D and 3D technology and applications, we will review these test challenges and their
emerging solutions in detail. In particular, we will focus on 3D probing, 3D design-for-test (including the IEEE P1838
standard-under-development), and test flow cost optimization.
Required background: electrical and/or computer engineering.
Basic understanding of test technology concepts: defects, fault models, design-for-test (especially scan
design and standard IEEE Std 1149.1 and IEEE Std 1500), test equipment, and wafer probing.
Suggested reading:
Overview paper on 3D test and DfT:
Erik Jan Marinissen, ‘Challenges and Emerging Solutions in Testing TSV-Based 2.5D- and 3D-Stacked ICs’,
Design, Automation, and Testing in Europe (DATE'12), Dresden, Germany, March 2012, pp. 1277-1282, DOI:10.1109/DATE.2012.6176689
Text books on test technology
Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, ‘Digital Systems Testing & Testable Design’, IEEE Press,
January 1993, ISBN 0780310624 (652 p.)
Alfred L. Crouch, ‘Design-For-Test For Digital ICs and Embedded Core Systems’, Prentice Hall, June 1999,
Prentice Hall; ISBN 0130848271 (347 p.)
Michael L. Bushnell and Vishwani D. Agrawal, ‘Essentials of Electronic Testing’, Kluwer Academic Publishers,
October 2000, ISBN 0792379918 (712 p.)
Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen (eds.), ‘VLSI Test Principles and Architectures – Design for Testability’,
Elsevier Morgan Kaufmann, July 2006, ISBN 0123705975 (777 p.)
Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba (eds.), ‘System-on-Chip Test Architectures’, Elsevier Morgan Kaufmann,
November 2007, ISBN 012373973X (896 p.)
DfT standards
IEEE Standards Association, ‘IEEE Std 1149.1TM-2013, IEEE Standard Test Access Port and Boundary-Scan Architecture’, IEEE,
New York, NY, USA, May 2013, DOI:10.1109/IEEESTD.2013.6515989
Kenneth P. Parker, ‘The Boundary-Scan Handbook’, Springer-Verlag, third edition, June 2003, ISBN 1402074964 (365 p.)
IEEE Standards Association, ‘IEEE Std 1500TM-2005, IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits’, IEEE,
New York, NY, USA, August 2005, DOI:10.1109/IEEESTD.2005.96465
Francisco da Silva, Teresa McLaurin, and Tom Waayers, ‘The Core Test Wrapper Handbook – Rationale and Application of IEEE Std 1500TM’,
Volume 35 of Frontiers in Electronics Testing, Springer-Verlag, Boston, MA, USA, 2006, ISBN 0387307516 (275 p.)
Comprehensive understanding of the challenges and emerging solutions in testing 2.5D- and 3D-stacked integrated
circuits.
