Production Testing of Digital SOCs and New Challenges

Adit Singh  - Auburn University, USA

Abstract :

This tutorial covers the core concepts in digital IC and SOC testing, including the types and frequency of defects introduced by VLSI manufacturing and the challenges and costs incurred in screening out defective parts during post manufacturing tests. Test pattern generation for detecting hard functional failures, as well as performance/timing failures, will be explained, alongside key design-for-test (DFT) techniques that dramatically improve the efficiency of test application. Significant new challenges being faced in achieving the extremely low defective parts per million (DPPM) levels required by state-of-the-art SOCs will also be discussed, along with the new test approaches, such as system level tests, being employed to meet these goals.

Part 1: Introduction and Motivation (50 mins)

  • VLSI Manufacturing and Test Flow
  • The Exponential Complexity of Test
  • Manufacturing Yield, Test Coverage and Product Quality
  • Defect Types and Statistics
  • Types of Tests during the Product Lifecycle
  • Test Economics

Part 2: Digital Test Basics (50 mins)

  • Test Definition
  • Defects, Faults and Errors
  • Fault Models: Stuck-at Faults
  • Fault Collapsing and Redundant Faults
  • Two-pattern Timing Tests
  • ATPG Test Pattern Generation

Part 3: Key Test and Design-for-Test (DFT) Methodologies (50 mins)

  • Scan DFT
  • Test Compression
  • Built-in Self Test (BIST)
  • Memory BIST
  • Boundary Scan and SOC Testing

Part 4: Recent Advances in Test (50 mins)

  • Defect Oriented Cell Aware Testing
  • Adaptive Testing
  • Functional System Level Tests
  • In Field Testing
  • Conclusion Q&A