Test and Trust of Secure Devices

Giorgio Di Natale , Université Grenoble Alpes, CNRS, Grenoble-INP, TIMA, FR

Abstract

Manufacturing testing is a critical step in the production process of integrated circuits (ICs) to ensure their quality and reliability. The most efficient and cost-effective solution for digital testing is based on the use of scan-chains. However, this solution poses security risks, as malicious users can exploit the test infrastructure to gain unauthorized access to secret information stored within the IC. The tension between scan-based Design-for-Testability (DfT) and security arises from their opposing objectives: improving controllability and observability of internal states for enhanced testability, and preventing control or observation of these internal states for increased security.

This lecture will explore solutions from the literature to counteract potential attacks that target the misuse of scan chains and other test infrastructures and standards, including IEEE 1149, 1500, and 1687. It will also address trust issues in the manufacturing of ICs, by providing insights into the possible threats related to outsourcing various manufacturing steps, including testing. The lecture will conclude with an overview of techniques used to mitigate trust issues and ensure the security and integrity of ICs throughout the manufacturing process. By combining testing and trust considerations, this lecture aims to provide a comprehensive understanding of the challenges and solutions in IC production.