People
Lecturers
Ahmad-Reza Sadeghi
Lejla Batina
Joan Daemen
Giorgio Di Natale
Marc Witteman
Jean-Pierre Seifert
Ramesh Karri
Jeyavijayan "JV" Rajendran
Scientific Committee Chairs
Elena-Ioana Vatajelu
Hussam Amrouch
Ahmad-Reza Sadeghi
TU Darmstadt, DE
Biography
Ahmad-Reza Sadeghi is a professor of Computer Science and the head of the System Security Lab at the Technical University of Darmstadt, Germany. He has led several Collaborative Research Labs with Intel since 2012 and Huawei since 2019.
He has studied Mechanical and Electrical Engineering and holds a Ph.D. in Computer Science from the University of Saarland, Germany. Before academia, he worked in the R&D of IT enterprises, including Ericsson Telecommunications. He has continuously contributed to the field of security and privacy research. He was Editor-In-Chief of IEEE Security and Privacy Magazine and had been serving on the editorial board of ACM TODAES, ACM TIOT, and ACM DTRAP.
He received the renowned German "Karl Heinz Beckurts" award for his influential research on Trusted and Trustworthy Computing. This award honors excellent scientific achievements that have significantly impacted industrial innovations in Germany. In 2018, he received the ACM SIGSAC Outstanding Contributions Award for dedicated research, education, and management leadership in the security community and pioneering contributions in content protection, mobile security, and hardware-assisted security. In 2021, he was honored with the Intel Academic Leadership Award at the USENIX Security Conference for his influential research on cybersecurity, particularly hardware-assisted security. In 2022 he received the prestigious European Research Council (ERC) Advanced Grant.
Recently, Ahmad-Reza Sadeghi has been diagnosed with a severe allergy to papers and discussions related to blockchains and cryptocurrencies.
Lejla Batina
Radboud University of Nijmegen, NL
Biography
Lejla Batina is a professor in embedded systems security at the Radboud University in Nijmegen, the Netherlands. She received her Ph.D. from KU Leuven, Belgium (2005) and prior to that she worked as a cryptographer for Pijnenburg Securealink in The Netherlands (2001u20132003). She has coauthored more than 160 refereed articles on various topics in applied cryptography and embedded system security. Her current research interests include physical attacks on cryptographic implementations and the impact of AI on hardware security.
She is a senior member of IEEE and an Editorial board member of top journals in security, such as IEEE Transactions on Information Forensics and Security and ACM Transactions on Embedded Computing Systems. She was program co-chair of CHES 2014, ACM WiSec 2021, Africacrypt 2022, SPACE 2020-2022, ACNS2024 and she co-organized (as general chair) IACR flagship conferences such as EUROCRYPT (2020-2021) and Real-world crypto symposium (RWC) 2022. Her research group at Radboud consists of 10+ researchers and 12 Ph.D. students have so far graduated under her supervision.
Joan Daemen
Radboud University of Nijmegen, NL
Biography
Joan Daemen is full professor symmetric cryptography at the Radboud University of Nijmegen, the Netherlands. He is co-designer of the influential Rijndael block cipher, that was selected by NIST as the Advanced Encryption Standard in 2000 and co-designer of the Keccak cryptographic hash function that was selected as the SHA-3 hash standard by NIST in 2012 and is a founder of permutation-based cryptography. He has over 20 years of security industry experience, including work as a security architect and cryptographer for STMicroelectronics. In 2017 he won the Levchin Prize for Real World Cryptography "for the development of AES and SHA3". In 2018 he was awarded an ERC advanced grant for research on the foundations of security in symmetric cryptography called ESCADA.
Giorgio Di Natale
TIMA Laboratory, FR
Biography
Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He works as Director of Research for the French National Research Center (CNRS), and he is the director of the TIMA laboratory in Grenoble since January 2021.
His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, and VLSI testing. He has published 2 books and 9 book chapters, 50+ journal papers, and more than 150 conference and symposium papers in these domains.
He has been involved in projects funded by the EU, Italy and France. He has been the action chair of the COST Action TRUDEVICE (Trustworthy Manufacturing and Utilization of Secure Devices), the biggest European research network on hardware security and trust.
He also actively contributed in the organization of the main international conferences in his domain (general chair of DATE20, program chair of DATE17, steering committee member of ETS, program chair of ETS16, member of organizing committee of ETS and VTS since 2010). He belongs to the program committees of many conferences (DATE, ETS, IOLTS, DSD, DTIS, FDTC, GLSVLSI, HOST, CS2) and he serves as associate editor for IEEE Transactions on CAD and IEEE Transactions on Computers.
He served as chair of the IEEE Computer Society TTTC, he is Golden Core member of the Computer Society and Senior member of the IEEE.
Marc Witteman
Riscure, NL
Biography
Marc Witteman has a long track record in the security industry. He has been involved with a variety of security projects for over three decades and worked on applications in mobile communications, payment industry, identification, and pay television. Recent work includes secure programming and mobile payment security issues.
He has authored several articles on embedded device security issues and he has extensive experience as a trainer, lecturing security topics for audiences ranging from novices to experts. As a security analyst he co-developed several tools for testing hardware and software security.
Marc has an MSc in Electrical Engineering from the Delft University of Technology in the Netherlands. From 1989 till 2001 he worked for several telecom operators, the ETSI standardization body and a government lab.
In 2001 he founded Riscure, and in almost two decades he developed the company into a world renowned security test lab and security test tool vendor. In 2010 Marc started Riscure Inc, the US branch of Riscure, based in San Francisco, and in 2017 he added a branch office in Shanghai. Being a technical entrepreneur, he holds both the CEO and CTO role at Riscure.
Jean-Pierre Seifert
Technische Universität Berlin and Einstein Foundation
Biography
Jean-Pierre Seifert studied computer science and mathematics at Johann-Wolfgang-Goethe-University at Frankfurt/Main. He received the Ph.D. degree from Johann-Wolfgang-Goethe-University at Frankfurt/Main, in 2000, under the supervision of Prof. Dr. C. Schnorr, one of the most important theoretician in the field of secure information systems. He gained intensive practical experience working in the research and development departments for hardware security at Infineon, Munich, and Intel, USA. At Intel, from 2004 to 2006, he has been responsible for the design and integration of new CPU security instructions for microprocessors that are going to be integrated in all Intel microprocessors. From 2007 to 2008, he developed for Samsung Electronics the worldwide first commercial secure cell phone based on the Linux operating system. Since 2008, he has been a Professor heading the group Security in Telecommunications, Technical University of Berlin (TU Berlin). This professorship is at the same time related with the management of the identically named research field at Telekom Innovation Laboratories, the research and development institute of Deutsche Telekom at TU Berlin. He holds more than 40 patents in the field of computer security. In 2002, he has been honored by Infineon with the award Inventor of the Year and received two Intel Achievement Awards, in 2005, for his new CPU security instructions for the Intel microprocessors.
Ramesh Karri
Tandon School of Engineering, New York University
Biography
Ramesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.
He has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).
He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS ( cyber.nyu.edu ), co-founded the Trust-Hub ( trust-hub.org /) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, ( www.nyu.edu/csaw2016/csaw-embedded ).
He co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).
He was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).
Jeyavijayan "JV" Rajendran
Texas A&M University
Biography
Jeyavijayan (JV) Rajendran (Senior Member, IEEE) received the Ph.D. degree from New York University, New York, NY, USA, in August 2015.,He is an Assistant Professor with the Department of Electrical and Computer Engineering, Texas A&M University at College Station, College Station, TX, USA. Previously, he was an Assistant Professor with The University of Texas at Dallas, Richardson, TX, USA, from 2015 to 2017. His research interests include hardware security and computer security.,Dr. Rajendranu2019s research has won the NSF CAREER Award in 2017, the ACM SIGDA Outstanding Young Faculty Award in 2019, the ACM SIGDA Outstanding Ph.D. Dissertation Award in 2017, and the Alexander Hessel Award for the Best Ph.D. Dissertation in the Electrical and Computer Engineering Department at NYU in 2016, along with several best student paper awards.