The ever increasing pressure to reduce production test costs of highly integrated devices is today leading to the adoption of design-for-test techniques for most common mixed-signal/RF circuits. In addition to classical techniques for facilitating access to embedded components, built-in test techniques have gained acceptance despite the additional costs in terms of silicon overhead and test errors. These advanced techniques may include on-chip test structures to monitor circuit performance while alleviating the complexity of test equipment or complete built-in self-test techniques.

The lecture starts by reviewing the fundamentals of mixed-signal/RF design-for-test, including the classical techniques for facilitating access to embedded modules and the basic principles for on-chip test signal generation and test response analysis. An evaluation of test quality at the design stage is essential for choosing specific built-in test structures. The traditional approach for digital circuits based on the use of fault models and fault simulation is not feasible for most common mixed-signal/RF devices. Instead, the lecture presents statistical techniques for the estimation of parametric test metrics.

Statistical learning is also at the origin of indirect test techniques. This generic approach aims at inferring the outcome of standard specification-based tests from a set of low-cost measurements provided by embedded test structures, sensors or monitors, that are easy to integrate and ideally transparent to device functionality. Furthermore, embedded sensors can also be used to enhance device yield and performance. The lecture illustrates the use of statistical learning for the test and control of mixed-signal/RF devices.

Finally, the lecture will present advanced built-in test techniques for most common mixed-signal devices, including converters, PLLs, RF circuits, and MEMS devices.