Embedded Test: From Test Compression to Logic Built-In Self-Test

The rapid scaling of semiconductor devices along with technological innovations allow designers to embed more than 100 million gates running in the GHz range. Testing designs of this complexity is a significant challenge. Not only more and more stringent quality requirements have to be satisfied but also the cost of test and design cycles are subjected to strong competitive pressures.

This lecture will focus on some of the advances shaping the test industry to address design and process changes. In particular, we will present state-of-the-art design-for-test (DFT) methodologies and practices for high-quality low-cost manufacturing test. Test compression was one of the important innovations introduced 12 years ago to reduce the cost of test. It started with a modest 10X reduction of volume and test data. Gradually, over the last 12 years, it has reached a 100X compression. Going forward the semiconductor industry is looking for even higher levels of compression to accommodate lager and lager designs and new types of fault models.

There are growing numbers of applications such as automotive electronics that require system level test. In addition to scan-based testing and issues related to at-speed testing in scan environment, the lecture will cover guidelines for design of built-in self-testable cores, techniques for random pattern testability, as well as BIST architectures for random logic. The lecture will also highlight, from a DFT perspective, methods deployed both to control test power dissipation and to reduce a negative impact of unknown states on test quality.

Finally, we will illustrate applications and discus future trends of DFT technology.

  1. Introduction- Current design trends and quality requirements
    1. Design characteristics, semiconductor technology trends
    2. Quality and productivity requirements
    3. Challenges facing logic test
    4. Defects and fau.t models
    5. Test quality – how is it measured
  2. Scan-based designs
    1. Logic-to-pin ratio, circuit complexity, test generation time
    2. Scan cells, multiplexing of data flip-flops, impact on performance, modes of operation, generic scan path, parallel scan chains,
    3. Test application time, safe scan shifting, volume of test data,
  3. At-speed scan-based test
    1. Single clock domain - single capture, over-testing, speed of loading, timing in capture window, frequency to reduce power and constraints on BIST controller,
    2. Frequency to reduce test time, double capture, launch from a semi-legal state, slow scan enable,
    3. multiple clock domains, at-speed testing within and between clock domains, clock suppression, hold states, multiple frequencies - single capture.
  4. Embedded test compression for deterministic test
    1. Analysis of requirements
    2. Basic architecture
    3. Compression schemes
    4. LFSR reseeding, solving linear equations,
    5. Stimuli generators – different types and their properties, linear dependencies and phase shifters
    6. On-chip compactors of test responses, time compactors (signature analysis, arithmetic accumulation, counting), space compactors (XOR trees, error code-based), finite memory compactors, error models and aliasing, aliasing probability, Markov model, transient period
    7. Handling of X states
    8. Power management in shift and capture
  5. Logic BIST –implementation and industrial practices
    1. Requirements for system test
    2. STUMPS LBIST architecture
    3. BIST-ready cores
    4. Test point insertion
    5. Generation of pseudorandom test patterns, test sequence aperiodicity, structural and linear dependencies, driving large number of scan chains
    6. Generators of pseudorandom sequences, linear feedback shift registers (LFSRs), primitive characteristic polynomials, m-sequence, principle of superposition, hybrid LFSR and cellular automata, ring generators, two-dimensional generators, phase shifter synthesis, weighted pseudo-random patterns, low transition PRPG
    7. Signature analyzers, Multiple input signature register (MISR) Parallel data acquisition, multiple error injections, unknown (X) states and their sources, X states and signatures, X-masking schemes, X-bounding logic
    8. At-speed test
    9. LBIST controllers
  6. Hybrid schemes – EDT and LBIST
    1. Dual generators/decompressors
    2. Signature registers/compactors
    3. Power management in shift and capture
    4. Test scheduling
    5. Clock gating, low-transition test pattern generators
    6. IJTAG and pattern retargeting for EDT and LBIST
    7. Applications
  7. Hierarchical test
    1. Need for hierarchical test methodology
    2. DFT implementation to facilitate hierarchical test
    3. Re-usable test patterns
    4. Pattern retargeting
    5. Bandwidth management
    6. Applications
  8. Conclusions
Janusz Rajski

Janusz Rajski

Lecturer