Fault modeling, fault simulation and ATPG

Fault simulation and automatic test pattern generation (ATPG) are essential steps of test preparation for digital integrated circuits (ICs). While fault simulation is used to estimate the quality of an existing collection of test patterns (test set), ATPG is used to produce high-quality test patterns. Typical ATPG algorithms work iteratively: they generate patterns, run fault simulation to determine whether the quality of the test set obtained so far is sufficient, and produce more patterns if required.

Both fault simulation and ATPG are defined with respect to a fault model. A fault is a model of a defect which could have occurred during the manufacturing of an IC. The modeling often implies abstraction, i.e., important behavioral details of low-level defective circuit behavior are not considered to reduce the complexity of fault simulation and ATPG. Different fault models are supposed to model different classes of actual defects with different degrees of accuracy.

In the age of Nanoscale Integration (NSI), state-of-the-art integrated circuits with gate length far below 100 nm consist of hundreds of millions of transistors. This implies new challenges for their reliability. Typical defects encountered in today's technologies are so-called spot defects that may cause opens and/or shorts at one or more of the different conductive levels of the devices. Furthermore, given the massive process variations of end-of-the-roadmap CMOS circuits timing and timing-related defects play an increasingly important role. Test generation for any type of defect is obviously not feasible due to the huge amount of CPU time and memory size required. Instead, test generation relies on fault models that are supposed to do both, i.e. to represent the defect behavior in an adequate way and to allow efficient ATPG and fault simulation for circuits of reasonable size.

The lecture starts by introducing basics of fault simulation and ATPG. Then we present modeling approaches and efficient test algorithms for fundamental NSI defect mechanisms enabling the handling of industrial multi-million-gate circuits. We finish with a discussion of further challenges for test algorithms in the nanoscale age.

Classical fault models, stuck-at faults, redundancy, fault simulation, automatic test pattern generation (ATPG), fault coverage, fault efficiency, defective parts per million (DPPM)
2.Defect-based test (DBT) and fault models
Shorts, opens, (enhanced) conditional multiple stuck-at ((E)CMS@) fault model, delay fault models, ATPG requirements, SAT-based ATPG
3.Test algorithms for static fault models
(E)CMS@ fault model, gate-exhaustive tests, shorts, opens, layout extraction and preprocessing, simulation, explicit test generation for opens, handling of unkowns
4.Test algorithms for delay faults
Path generation, sensitization conditions, waveform-based delay ATPG, variation-aware test
5.Outlook: Test algorithms in nanoscale
Variation awareness, early life failures, ATPG and optimization goals
Basic understanding of logic circuits and testing problems, introductory ideas of VLSI technology, see e.g. N. Jha, S. Gupta, "Testing of Digital Systems", Campridge University Press, 2003, ISBN
In a first step fundamentals on testing problems with a focus on fault simulation and ATPG are recalled. Participants are aware of new challenges for the test of nanoscale electronics. In particular, they have a precise knowledge of advanced fault models used to better capture the actual physical defect mechanisms and the low-level behavior of the defective circuits. On the other hand side they understand how these models can be lifted to the logical level to allow efficient fault simulation and ATPG algorithms for industrially sized circuits. Finally, they have some insight into the fundamental changes necessary for variation aware test algorithms.