Defect based testing

Spot defects such as opens and shorts defects are responsible for a large percentage of failures in CMOS technologies. In today deca-nanometer technologies with very dense interconnect structures, their impact is expected to increase. In this presentation a survey of the key developments in modelling open and short defects are presented including particular types of defects such as floating gate and gate oxide short. Their implications in the test generation process are analyzed. An overview of the historical developments of these models is proposed starting from the classical stuck-at and stuck-open models till the new more realistic models that take into account the unpredictable parameters of the defect such as resistance, location, size... The logic detectability of defects taking into consideration these unpredictable parameters is explored. The concept of Detectability Interval (DI) is described together with its applicability to the test generation process with the objective of improving the quality of the test vectors.
  1. Test with Classical Fault Models
    • Stuck-at
    • Wired-OR
    • Wired-AND
    • Dominant
    • Stuck-Open
  2. Diagnosis with Classical Fault Models
    • Stuck-at
    • Wired
  3. Realistic Fault Models
    • Voting
    • Biased Voting
    • Direct Voting
  4. Analysis of Realistic Defects
    • Resistive short
    • Resistive Open
    • Floating gate
    • Gate Oxide Short
  5. Test with Realistic Defect Models
    • Detection Interval
    • Global Detection Interval
    • Efficiency metrics
  6. Application to the Test Generation process
    • Fault Simulation with intervals
    • ATPG with intervals
Basic concepts of: digital testing with fault model, classical fault models (stuck-at, bridging), fault simulation, ATPG
Advanced concepts of: defect modeling, defect based testing