Production test practices - How they vary and why?

The main goal of semiconductor production test is identifying failing parts, which involves tradeoffs between quality, cost, schedule, flexibility, risk and available resources. The tradeoffs depend e.g. on target application, volume, and product maturity. Similarly, applicable test practices, such as adoption of DFT & BIST, multi-site test, partitioning of test content across test insertions, depend on package type, volume, chip functionality, value chain, product mix, skill set, and many more. As a result, test practices vary widely across companies and even across product groups within the same company, driven by a large number of influencing factors.

Without knowing these influencing factors, practices reported from industry will appear confusing or contradictory, especially to newcomers. The (academic) test literature has a tendency to single out one specific aspect without putting it into a broader perspective. Furthermore, the components and capabilities of the test cell / ATE are generally not well understood and are therefore not considered as part of the solution space for test innovation. This makes it very difficult for newcomers to come up with a comprehensive mental model of the test landscape that enables them (1) judging which problems are how relevant in which cases and (2) assessing how practical proposed solution will be in a given context.

This lecture will present a framework to think about the goals in test, the influencing factors, and test practices that are deployed or proposed. A simple test cost model will be presented. The building blocks and capabilities of the test cell and the ATE will be explained. Examples will illustrate the links between test practices and influencing factors.

  • The role of test: Identify bad parts, trimming, feedback to design / library
  • Goals and constraints
    • Quality, risk
    • Test cost
    • Time-to-Volume
    • Resources: tester capabilities, tester capacity
    • Flexibility: product mix, process excursions
    • Manpower, skills
  • Some context
    • Who is involved? - Test engineer, designer, DFT engineer, product engineer, test operator
    • Some example test lists
    • Test cell: wafer prober / handler, ATE, probe card / load board
    • ATE:
      • Instruments & capabilities: digital channels, device power supplies, arbitrary waveform generators & digitizers, RF source & receiver
      • Per-pin resources vs shared resources, universal pin, time measurements, protocol-aware ATE
      • Clocking and synchronization
      • Data-path and computation, local processing
      • Scaling with Moore’s law
      • Test program generation, test program management
    • Test cost model: Capital cost (ATE and wafer prober / handler), test time, operating cost, equipment utilization, probe cards, multi-site test, concurrent test, DFT silicon area
  • Influencing factors
    • Target market: Consumer, automotive, medical, industrial, …
    • High performance or low-end consumer
    • High volume vs high mix
    • Product life cycle: Characterization, early production ramp, volume production
    • Value chain: IDM vs design house & test house, who owns the testers?
    • Is there a DFT team as part of the design team or as part of the test department?
    • Package: packaged die, multi-chip module / 2.5D / 3D, wafer scale package, bare die
    • Test insertion: Wafer test vs partial assembly test vs final test, hot vs cold
    • New or mature process, design margin
    • New vs incremental design/IP
    • Chip content: Digital, memory, HSIO, mixed-signal, RF, MEMS
    • Seasonality: Christmas, ChinThe role of test: Identify bad parts, trimming, feedback to design / library
  • Goals and constraints
    • Quality, risk
    • Test cost
    • Time-to-Volume
    • Resources: tester capabilities, tester capacity
    • Flexibility: product mix, process excursions
    • Manpower, skills
  • Some context
    • Who is involved? - Test engineer, designer, DFT engineer, product engineer, test operator
    • Some example test lists
    • Test cell: wafer prober / handler, ATE, probe card / load board
    • ATE:
      • Instruments & capabilities: digital channels, device power supplies, arbitrary waveform generators & digitizers, RF source & receiver
      • Per-pin resources vs shared resources, universal pin, time measurements, protocol-aware ATE
      • Clocking and synchronization
      • Data-path and computation, local processing
      • Scaling with Moore’s law
      • Test program generation, test program management
    • Test cost model: Capital cost (ATE and wafer prober / handler), test time, operating cost, equipment utilization, probe cards, multi-site test, concurrent test, DFT silicon area
A general understanding of electronics is assumed. Attendees are encouraged to submit questions about real-life testing. The author will attempt to cover them as part of the lecture.

Attendees will learn what determines the relative importance of test goals (quality, cost, schedule, flexibility) and what influences the adoption of test practices (BIST, multi-site test, functional test, ...). They will obtain a more holistic mental model of the test landscape to assist them judging which problems are important to be solved and which solutions have a chance of actually being deployed.

They will learn about the components and capabilities of the test cell and ATE.