Jochen Rivoir is a company fellow at Advantest. He has been working in R&D of electronic instruments and in research on semiconductor test since 1985 at Hewlett-Packard, Agilent Technologies, Verigy, and now Advantest.
From 1999 to 2001 he managed the SOC-Testing research group at Agilent Laboratories, Palo Alto, US. Since then he contributes as test system architect in strategic R&D in Germany to future test solutions. He has been engaged in test methodology discussions with many companies. His specific interest is in innovative generic solutions to mixed-signal / RF test challenges. Since 2009, he has won 4 company innovation awards. He is listed on 32 granted patents related to test and has additional 20 patent applications pending. He has been invited to 11 panel discussions and has published more than 30 papers. He is on the steering committee of ETS and serves as a reviewer for ATS, DATE, ITC, JETTA, TVHSAC, VTS, WTW, ZuE, Test Vision 2020, TODAES.