Janusz Rajski received the M.S. degree in electrical
engineering from the Technical Uni-versity of Gdansk,
Gdansk, Poland, in 1973, and the Ph.D. degree in electrical
engineering from the Poznan University of Technology,
Poznan, Poland. He is a chief scientist and the director of
engineer-ing for the Silicon Test Solutions products group
at Mentor Graphics. He has published more than 200 research
papers in these areas and is co-inventor of 80 US patents.
He is also the principal inventor of Embedded Deterministic
Test (EDT(tm)) technology used in the first commercial test
compression prod-uct TestKompress(R). He was co-recipient of
the 1993 Best Paper Award for the paper on logic synthesis
published in the IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, co-recipient of the 1995
and 1998 Best Paper Awards at the IEEE VLSI Test Symposium,
co-recipient of the 1999 and 2003 Honorable Mention Awards
and the 2012 Most Significant Paper Award at the IEEE
International Test Conference, co-recipient of the 2010 Best
Paper Award at the IEEE European Test Symposium,
co-recipient of the 2008 Best Paper Award at the Asian Test
Symposium, and 2009 Best Paper Award at the VLSI Design, as
well as co-recipient of the 2006 IEEE Circuits and Systems
Society Donald O. Pederson Outstanding Paper Award
recognizing the paper on embedded deterministic test
published in the IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems. He served as Program
Chair of the IEEE International Test Conference. In 2009 he
received the Stephen Swerling Innovation Award from Mentor
Graphics "for his breakthrough innovation, TestKompress, and
his many contributions to revitalizing Mentor's DFT business
to its current position as #1 test business in EDA"". In 2011
Janusz was elevated to the grade of IEEE Fellow for
"contributions to VLSI circuit testing and test
compression". In 2013 he was awarded an honorary doctorate
from the Poznan University of Technology, Poznan, Poland..
