Circuit Reliability Estimation using Machine Learning and Brain-Inspired Algorithms

Hussam Amrouch  - University of Stuttgart, DE

Abstract :

In advanced technology nodes, transistor performance is increasingly impacted by different types of design-time degradation (caused by manufacturing variability) and run-time degradation (caused by temperature and aging effects). Both types of degradation seriously impact the underlying electrical properties of transistors such as threshold voltage. To estimate the impact of degradations on a complete circuit, extensive SPICE simulations have to be performed. However, for large circuits and full processors, the computational effort of such simulations may become infeasible very quickly. Furthermore, such simulations may not be easily delegated to circuit designers because the required transistor models cannot be shared due to their high confidentiality for the foundry. In this lecture, we tackle these challenges at multiple levels, ranging from transistor to memory to circuit and system level. We will explain how we can employ machine learning and brain-inspired algorithms to overcome computational infeasibility and confidentiality problems, paving the way towards design close to the edge, which is especially important for advanced technology nodes. Further, we will explain how the reliability of emerging beyond-CMOS technologies such as Ferroelectric Transistors (FeFET) can be modeled in order to enable effective HW/SW codesign which is inevitable for building deep neural networks that are robust against reliability degradations.Syllabus

Sylabus :

The lecture will cover the following topics:

  • Brain-inspired Hyperdimensional computing
  • Machine Learning
  • Transistor Aging and Self-Heating
  • Circuit and SRAM Reliability
  • Graph Neural Networks
  • HW/SW codesign