Advanced integrated circuits fabricated in highly scaled technologies are susceptible to microscopic manufacturing flaws and defects that cannot be completely eliminated in even the best controlled fabrication processes. Consequently, many (for some designs, even the majority) of the ICs manufactured are defective, in that they fail to meet their full functional specifications. All manufactured parts must be carefully tested to screen out defective circuits before they are integrated into boards and systems. Unfortunately, comprehensive testing of complex ICs containing billions of circuit components but limited to only a few dozen wires for external access is extremely challenging and time consuming. Furthermore, while the manufacturing cost per transistor for an IC has declined exponentially over the past several decades in keeping with Moore's Law, test costs per transistor have declined only linearly, leading to the situation today where test costs make up a very substantial part of overall manufacturing costs for an increasing number of high end ICs. The economic viability of several emerging design and packaging technologies now critically depends on the development of more effective and efficient test methodologies. Meanwhile, our increasing dependence on electronics in all aspects of daily life, including for many safety critical control applications, has significantly raised the reliability levels demanded by users. Most notably, the automotive industry has set a "zero defect" quality target for vehicular electronics. All these factors contribute to the central role that test technology plays in the microelectronics and semiconductor industries.

The exponential complexity of test in the case of digital circuits is obvious: its takes 2**n input combinations to exhaustively test an n-input combinational circuit. Large circuits today can easily have a hundred or more inputs. Even if the test inputs are applied at a gigahertz rate, a billion inputs every second, it will take trillions of centuries of test time (dramatically higher for the more realistic case of sequential designs) to complete a test that covers the entire input space for such a circuit. Clearly, realistic tests can explore only an infinitesimal fraction of the input space. This makes test selection critically important. Practical, cost effective testing involves applying tests that target "likely" defects. Unfortunately, these are not always easy to identify for complex designs, manufactured through complicated, multi-stage fabrication processes, which are further subject to some degree of normal process drifts and, occasionally, larger, more significant, excursions. Clearly, for complex, high end parts, testing is statistical and cannot absolutely guarantee a defect free IC. The primary goal of test methodologies is to most cost effectively test a part to ensure desired levels of product quality and reliability. Increasingly, test is also being used to detect and diagnose repeated (systematic) failures in manufactured ICs so that the root cause of the failures can be identified and eliminated. This results in higher yields and more efficient manufacturing, a major productivity driver for expensive high end circuits.

This introductory session of the Test Summer School provides the basic background, motivational overview and context for the more in depth study of the testing topics presented in subsequent lectures. The presentation will open with a brief overview of microelectronics technology, including circuit structures, IC design and layout, and fabrication processes. This will provide the background for a discussion on manufacturing defects and their impact on circuit behavior leading, ranging from degraded performance to catastrophic failure. The different types of testing performed at various stages of IC manufacturing, system assembly and field deployment will be discussed, along with the test effectiveness (coverage) needed to deliver the desired product quality and reliability. Defect statistics and yield models will also be presented. The lecture will then move on to fault models that capture the impact of the erroneous electrical behavior of defects in terms of logical errors. The unique role and importance of the classical "stuck-at" fault model in testing will be explained. Other fault models that have been developed to cover electrical shorts (bridging fault model), opens (stuck-open model), and gate and circuit timing degradation (transition delay and path delay models) will also be presented. The importance of burn-in and other stress tests in screening out latent defects to ensure reliability in operation will be discussed. To motivate the subsequent sessions at the Test Sumer School, the lecture will conclude with a discussion of the complexity of combinational test generation, and the much more difficult problem of generating tests for sequential circuits that has led to the wide scale adoption of the scan design-for-test methodology.